1. Field of the Invention
The present invention relates to package structures, and more particularly, to an electronic device and a package structure thereof for improving power integrity.
2. Description of Related Art
Along with the progress of semiconductor processes, integrated circuits have been designed to operate at lower voltage and higher speed. Accordingly, power integrity has become a concern in IC packages. As the number of switches in a chip continuously increases and the supply voltage of the chip continuously decreases, power fluctuation seriously affects system operation. Therefore, stable and reliable power supplies have become a focus of research and development efforts.
Currently, power integrity is improved through using the decoupling capacitors. Since the conventional QFP (Quad Flat Package) and QFN (Quad Flat No Leads) packages cannot provide decoupling capacitors by themselves, the packages need externally connected decoupling capacitors so as to improve the power integrity.
FIG. 1A is a schematic cross-sectional view of a QFP package structure 1. Referring to FIG. 1A, the QFP package structure 1 has a circuit board 1b having a circuit layer 14, a ground layer 15 and a power layer 16, and a QFP package 1a disposed on the circuit board 1b. The QFP package 1a has a lead frame 10 having a die attach pad 101 and a plurality of leads 102, a semiconductor element 11 disposed on the die attach pad 101 and electrically connected to the leads 102 through a plurality of bonding wires 110, and an encapsulant 12 encapsulating the semiconductor element 11. The circuit layer 14 is formed at the outermost side of the circuit board 1b and has a ground pad 14a and a power pad 14b. The ground pad 14a is electrically connected to the ground layer 15 through a plurality of conductive through holes 141, and the power pad 14b is electrically connected to the power layer 16 through a plurality of conductive through holes 143. Further, the leads 102 are electrically connected to the power pad 14b. 
FIG. 1B is a schematic cross-sectional view of a conventional QFN package structure 1′. Referring to FIG. 1B, the QFN package structure 1′ has a circuit board 1b having a circuit layer 14, a ground layer 15 and a power layer 16, and a QFN package 1a′ disposed on the circuit board 1B. The package 1a′ has a lead frame 10′ having a die attach pad 101 and a plurality of leads 102′, a semiconductor element 11 disposed on the die attach pad 101 and electrically connected to the leads 102′ through a plurality of bonding wires 110, and an encapsulant 12 encapsulating the semiconductor element 11. In the QFN package structure 1′, the leads 102′ do not extend out from the package sides and the bottoms of the leads 102′ provide electrical connections to the circuit board 1b. The circuit layer 14 is formed at the outermost side of the circuit board 1b and has a ground pad 14a and a power pad 14b. The ground pad 14a is electrically connected to the ground layer 15 through a plurality of conductive through holes 141 and the power pad 14b is electrically connected to the power layer 16 through a plurality of conductive through holes 143. Further, the leads 102′ are electrically connected to the power pad 14b. 
However, referring to FIG. 1C, the conventional package structure 1, 1′ has a parasitic inductor L and a parasitic resistor R connected in series between the power and ground terminals. When the impedance of the parasitic inductor L increases with frequency, the impedance Z between the power and ground terminals also increases. As such, an IR drop or a ground bounce may be generated between the power and ground terminals and adversely affect the power integrity of the package structure.
To improve the power integrity, the package structure 1, 1′ needs at least an externally connected decoupling capacitor (not shown). The decoupling capacitor is generally mounted to the package structure through a SMT (Surface Mounted Technology) process. As such, the material cost and the fabrication cost are increased due to the decoupling capacitor and its SMT process.
Furthermore, the externally connected decoupling capacitor has another parasitic inductor (not shown) and another parasitic resistor (not shown), which increases the electrical loop between the power and ground terminals. In addition, the equivalent series resistance (ESR) and the equivalent series inductance (ESL) of the decoupling capacitor are large. Therefore, the package structure cannot achieve a high performance.
Therefore, how to overcome the above-described drawbacks has become urgent.